The present invention relates to an amplifier circuit for amplifying an electrical signal.
Conventionally, as a circuit configuration for operating at a high speed, such circuit having a high input capacitance (such as an analog/digital converter), a circuit has been proposed which includes a buffer amplifier unit in a cascade connected emitter follower arrangement.
FIG. 1 is the circuit diagram of an example of the conventional amplifier circuit (buffer amplifier).
In FIG. 1, an input terminal Pl is connected with a resistor 30 connected with the respective bases of an NPN transistor 31 and a PNP transistor 32. The emitter of the transistor 31 is connected with a negative power supply (-V) through a resistor 33, and the collector thereof is connected with a positive power supply (+V). The emitter of the transistor 32 is connected with the positive power supply (+V) through a resistor 35, and the collector thereof is connected with the negative power supply (-V) through a resistor 36. Further, the emitter of the transistor 31 is connected with the base of a PNP transistor 38 through a resistor 37, and the emitter of the transistor 32 is connected with the base of an NPN transistor 40 through a resistor 39. The collector of the transistor 38 is connected with the negative power supply (-V) through a resistor 41 and the emitter thereof is connected with the positive power supply (+V) through a resister 42 and also connected with an output terminal P2 through a resistor 43. The collector of the transistor 40 is connected with the positive power supply (+V) through a resistor 44, and the emitter thereof is connected with the negative power supply (-V) through a resistor 45 and also connected with the output terminal P2 through a resistor 46.
In operation, when an input signal is applied to the input terminal Pl, its in-phase signal component is outputted to the emitter of the transistor 31 whereas its anti-phase signal component is outputted to the emitter of the transistor 32. The output from the transistor 31 which is sent to the transistor 38 the output signal from which is outputted at the output terminal P2. Likewise, the output signal from the transistor 32 which is sent to the transistor 40 the output from which is outputted at the output terminal P2. The output signals from the transistors 38 and 40 are synthesized to provide the signal similar to the input signal at the output terminal P2. This circuit, which is connected in cascade with the emitter follower, can provide a high input impedance.
It should be noted that in order to remove D.C. current offset, the above conventional circuit configuration is provided with NPN type emitter followers (NPN transistors 31, 40) and a PNP type emitter followers (PNP transistors 32, 38) in cascade connection with each other. The NPN type emitter follower operates at a relatively high speed for the ascending signal which places the state between its base and emitter in a forward-biased state with a relatively high voltage whereas it operates a relative low speed for the descending signal which causes the state between its base and emitter to reach its reverse-biased state. On the other hand, the PNP type emitter follower operates at a relatively high speed for the descending signal whereas it operates at a relatively low speed for the ascending signal.
In this way, the circuit composed of the NPN emitter follower and the PNP emitter follower in cascade connection cannot operate at a high speed for both ascending and descending signals.